{"id":975,"date":"2011-03-02T23:05:13","date_gmt":"2011-03-02T13:05:13","guid":{"rendered":"http:\/\/brnz.org\/hbr\/?p=975"},"modified":"2011-03-04T22:43:28","modified_gmt":"2011-03-04T12:43:28","slug":"assembly-primer-parts-6-%e2%80%94-moving-data-%e2%80%94-arm","status":"publish","type":"post","link":"https:\/\/brnz.org\/hbr\/?p=975","title":{"rendered":"Assembly Primer Parts 6 \u2014 Moving Data \u2014 ARM"},"content":{"rendered":"

My notes for where ARM differs from IA32 in the Assembly Primer video Part 6 — Moving Data<\/a>.<\/p>\n

(There is no separate part 5 post for ARM — apart from the instructions, it’s identical to IA32. There’s even support for the .bss section, unlike SPU and PPC)<\/p>\n

Moving Data<\/h2>\n

We’ll look at MovDemo.s<\/a> for ARM. First, the storage:<\/p>\n

.data\r\n\r\n    HelloWorld:\r\n        .ascii \"Hello World!\"\r\n\r\n    ByteLocation:\r\n        .byte 10\r\n\r\n    Int32:\r\n        .int 2\r\n    Int16:\r\n        .short 3\r\n    Float:\r\n        .float 10.23\r\n\r\n    IntegerArray:\r\n        .int 10,20,30,40,50<\/pre>\n
It’s the same as for IA32, PPC and SPU. Like the first two, ARM will cope with the unnatural alignment.<\/p>\n
1. Immediate value to register<\/h3>\n
.text\r\n.globl _start\r\n_start:\r\n    @movl $10, %eax\r\n\r\n    mov r0, #10<\/pre>\n
Move the value 10 into register r0.<\/p>\n
Something to note: the ARM assembly syntax has some slightly differences. Where others use #<\/strong> to mark the start of a comment, ARM has @<\/strong> (although #<\/strong> works at the start of a line). Literal values are prefixed with #<\/strong>, which confuses the default syntax highlighting in vim.<\/p>\n
2. Immediate value to memory<\/h3>\n
    @movw $50, Int16\r\n\r\n    mov r1, #50\r\n    movw r0, #:lower16:Int16\r\n    movt r0, #:upper16:Int16\r\n    strh r1, [r0, #0]<\/pre>\n
We need to load the immediate value in a register (r1), the address in a register (r0) and then perform the write. To quote the Architecture Reference Manual:<\/p>\n
The ARM architecture … incorporates … a load\/store architecture, where data processing operations only operate on register contents, not directly on memory contents.<\/p><\/blockquote>\n
which is like PPC and SPU, and unlike IA32 — and so we’ll see similarly verbose alternatives to the IA32 examples from the video.<\/p>\n
I’m using movw<\/strong>, movt<\/strong> sequence to load the address, rather than ldr<\/strong> (as mentioned in the previous installment).<\/p>\n
strh<\/strong> is, in this case, Store Register Halfword (immediate)<\/strong> — writes the value in r1 to the address computed from the sum of the contents of r0 and the immediate value of 0.<\/p>\n
3. Register to register<\/h3>\n
    @movl %eax, %ebx\r\n\r\n    mov r1,r0<\/pre>\n
mov<\/strong> (Move<\/strong>) copies the value from r0 to r1.<\/p>\n
4. Memory to register<\/h3>\n
    @movl Int32, %eax\r\n\r\n    movw r0, #:lower16:Int32\r\n    movt r0, #:upper16:Int32\r\n    ldr r1, [r0, #0]<\/pre>\n
Load the address into r0, load from the address r0+0. Here ldr<\/strong> is Load Register (immediate)<\/strong>.<\/p>\n
5. Register to memory<\/h3>\n
    @movb $3, %al\r\n    @movb %al, ByteLocation\r\n\r\n    mov r0, #3\r\n    movw r1, #:lower16:ByteLocation\r\n    movt r1, #:upper16:ByteLocation\r\n    strb r0, [r1, #0]<\/pre>\n
Once again the same kind of thing — load 3 into r0, the address of ByteLocation into r1, perform the store.<\/p>\n
6. Register to indexed memory location<\/h3>\n
    @movl $0, %ecx\r\n    @movl $2, %edi\r\n    @movl $22, IntegerArray(%ecx, %edi, 4)\r\n\r\n    movw r0, #:lower16:IntegerArray\r\n    movt r0, #:upper16:IntegerArray\r\n    mov r1, #2\r\n    mov r2, #22\r\n    str r2, [r0, r1, lsl #2]<\/pre>\n
A little more interesting — here str<\/strong> is Store Register (register) <\/strong>which accepts two registers and an optional shift operation and amount. Here lsl<\/strong> is logical shift left<\/strong>, effectively multiplying r1 by 4 — the size of the array elements.<\/p>\n
(GCC puts asl<\/strong> here. Presumably identical to logical shift left, but there’s no mention of asl<\/strong> in the Architecture Reference Manual. Update:<\/strong> ASL is referenced in the list of errors here<\/a> as an obsolete name for LSL)<\/p>\n
Two source registers and a shift is still shy of IA32’s support for an calculating an address from a base address, two registers and a multiply.<\/p>\n
7. Indirect addressing<\/h3>\n
    @movl $Int32, %eax\r\n    @movl (%eax), %ebx\r\n\r\n    movw r0, #:lower16:Int32\r\n    movt r0, #:upper16:Int32\r\n    ldr r1, [r0, #0]\r\n\r\n    @movl $9, (%eax)\r\n\r\n    mov r2, #9\r\n    str r2, [r0, #0]<\/pre>\n
More of the same.<\/p>\n
Concluding thoughts<\/h2>\n
In addition to the cases above, ARM has a number of other interesting addressing modes that I shall consider in more detail in the future — logical operations, auto-{increment, decrement} and multiples. Combined with conditional execution, there are some very interesting possibilities.<\/p>\n
Other assembly primer notes are linked here<\/a>.
\n<\/a><\/h3>\n","protected":false},"excerpt":{"rendered":"
My notes for where ARM differs from IA32 in the Assembly Primer video Part 6 — Moving Data. (There is no separate part 5 post for ARM — apart from the instructions, it’s identical to IA32. There’s even support for the .bss section, unlike SPU and PPC) Moving Data We’ll look at MovDemo.s for ARM. … Continue reading “Assembly Primer Parts 6 \u2014 Moving Data \u2014 ARM”<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[5,26],"tags":[45,38],"_links":{"self":[{"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/posts\/975"}],"collection":[{"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=975"}],"version-history":[{"count":11,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/posts\/975\/revisions"}],"predecessor-version":[{"id":990,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/posts\/975\/revisions\/990"}],"wp:attachment":[{"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=975"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=975"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=975"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}