{"id":932,"date":"2011-02-12T00:21:58","date_gmt":"2011-02-11T14:21:58","guid":{"rendered":"http:\/\/brnz.org\/hbr\/?p=932"},"modified":"2011-02-12T00:21:58","modified_gmt":"2011-02-11T14:21:58","slug":"assembly-primer-parts-1-2-and-3-arm","status":"publish","type":"post","link":"https:\/\/brnz.org\/hbr\/?p=932","title":{"rendered":"Assembly Primer Parts 1, 2 and 3 — ARM"},"content":{"rendered":"

I had started a series of posts on assembly programming<\/a> for the Cell BE PPU and SPU, based on the assembly primer video series from securitytube.net<\/a>. I have recently acquired a Nokia N900, and so thought I might take the opportunity to continue the series with a look at the ARM processor as well.<\/p>\n

Wikipedia lists the N900’s processor as a Texas Instruments OMAP3430,\t600MHz \tARMv7 Cortex-A8. I’m not at all familiar with the processor family, so I’ll be attempting to find out what all of this means as I go :P<\/p>\n

I’ve set up a cross compiler on my desktop machine using Gentoo’s neat crossdev tool (built using crossdev -t arm-linux-gnueabi<\/strong>). The toolchain builds a functional Hello, World!<\/p>\n

(I note that scratchbox appears to be the standard tool\/environment used to build apps for Maemo — I may take a closer look at that at a later date)<\/p>\n

I have whatever the latest public ‘stable’ Maemo 5 release is on the N900 (PR 1.3, I think),\u00a0 with an apt-get install<\/strong> openssh<\/strong> gdb<\/strong> — thus far, enough to “debug” a functional Hello, World!<\/p>\n

What follows are some details of the Cortex-A8 architecture present in the N900, particularly in how it differs from IA32, as presented in the videos Part 1 — System Organisation<\/a>, Part 2 — Virtual Memory Organization<\/a> and Part 3 — GDB Usage Primer<\/a>. I’ve packed them all into this post because gdb usage and Linux system usage are largely the same on ARM as they are on PPC and IA32.<\/p>\n

Most of the following information comes from the ARM Architecture Reference Manual<\/a>.<\/p>\n

(The number of possible configurations of ARM hardware makes it interesting at times to work out exactly which features are present in my particular processor. From what I can tell, the N900’s Cortex-A8 is ARMv7-A and includes VFPv3 half, single and double precision float support, and NEON (aka Advanced SIMD). I expect I’ll find out more when I actually start to try and program the thing. As to which gcc -march, -mcpu or -mfpu options are most correct for the N900 — I have no idea.)<\/p>\n

1. Registers<\/h2>\n

Integer<\/h3>\n

There are sixteen 32bit ARM core registers, R0 to R15, where R0–R12 are for general use. R13 contains the stack pointer (SP), R14 is the link register (LR), and R15 is the program counter (PC).<\/p>\n

The current program status register (CSPR) contains various status and control bits.<\/p>\n

VFPv3 (Floating point) & NEON (Advanced SIMD)<\/h3>\n

There are thrirty two doubleword (64bit) registers, that can be referenced in a number of ways.<\/p>\n

NEON instructions can access these as thirty two doubleword registers (D0–D31) or as sixteen quadword registers (Q0–Q15), able to be used interchangeably.<\/p>\n

VFP instructions can view the same registers as 32 doubleword registers (again, D0–D31) or as 32 single word registers (S0–S31). The single word view is packed into the first 16 doubleword registers.<\/p>\n

Something like this pic (click to embiggen):<\/p>\n

\"\"<\/a><\/p>\n

VFP in this core (apparently) supports single and double precision floating point data types and arithmetic, as well as half precision (possibly in two different formats…).<\/p>\n

NEON instructions support accessing values in extension registers as<\/p>\n