{"id":724,"date":"2010-12-01T23:10:46","date_gmt":"2010-12-01T13:10:46","guid":{"rendered":"http:\/\/brnz.org\/hbr\/?p=724"},"modified":"2010-12-02T15:42:17","modified_gmt":"2010-12-02T05:42:17","slug":"assembly-primer-part-6-%e2%80%94-moving-data-%e2%80%94-ppc","status":"publish","type":"post","link":"https:\/\/brnz.org\/hbr\/?p=724","title":{"rendered":"Assembly Primer Part 6 \u2014 Moving Data \u2014 PPC"},"content":{"rendered":"

These are my notes for where I can see PPC varying from ia32, as presented in the video Part 6 \u2014 Moving Data<\/a>.<\/p>\n

There are notable differences between PPC and ia32 when moving\/copying data around, although not as much as is the case with SPU — PPC copes with non-natural alignments (although I’m not sure what performance penalties there are on Cell or modern ia32 arches for doing so — at the very least, the cost of the occasional extra cache line), but doesn’t have the full range of mov instructions supported by ia32.<\/p>\n

(When approaching this part, I wrote the SPU version first because I’ve had a lot more experience with that arch and I though it would be quicker. I was wrong.)<\/p>\n

Moving Data<\/h2>\n

So, let’s look at MovDemo.s<\/a> for PPC, piece by piece.<\/p>\n

First, the storage:<\/p>\n

# Demo program to show how to use Data types and MOVx instructions \r\n\r\n.data\r\n    HelloWorld:\r\n        .ascii \"Hello World!\"\r\n\r\n    ByteLocation:\r\n        .byte 10\r\n\r\n    Int32:\r\n        .int 2\r\n    Int16:\r\n        .short 3\r\n    Float:\r\n        .float 10.23\r\n\r\n    IntegerArray:\r\n        .int 10,20,30,40,50\r\n<\/pre>\n
Same as for ia32 and SPU.\u00a0 PPC will cope with the lack of alignment.<\/p>\n
1. Immediate value to register<\/h3>\n
.text\r\n    .globl _start\r\n    _start:\r\n        #movl $10, %eax\r\n        li 0,10\r\n<\/pre>\n
Simple enough to load a small constant into a register.\u00a0 Like SPU, there’s extra work required if trying to load more complex values.<\/p>\n
To load a full 32-bits of immediate data into a register requires two half-word load  instructions for the upper and lower parts (as will be seen for loading addresses).\u00a0 Loading 64-bit values appears to take five instructions<\/a> (four immediate loads and a rotate in the middle).\u00a0 The joys of 32-bit, fixed-length instructions :)<\/p>\n
Aside:\u00a0 li<\/em> and lis<\/em> are extended mnemonics that generate addi <\/em>and addsi<\/em> instructions — and if the second operand is zero, these instructions use the value zero, not the value in gpr0.\u00a0 Special case ftw.<\/p>\n
Speculating: On SPU, loads from local store take 6 cycles, so it will often be quicker to load a value than to generate it.\u00a0 On PPC, it would seem that even five instructions will complete much faster than a (potential) L2 cache miss.<\/p>\n
2. Immediate value to memory<\/h3>\n
#movw $50, Int16\r\n\r\nli 1,50\r\nlis 2,Int16@ha\r\naddi 2,2,Int16@l\r\nsth 1,0(2)\r\n<\/pre>\n
There’s no instruction to write an immediate value directly to memory — the source for a write must be a register, so we load that first.<\/p>\n
The address is loaded in the following two instructions — @l is the lower 16 bits of the address.\u00a0 @ha refers to the upper 16 bits of the address, where the a indicates the value is “adjusted so that adding the low 16 bits will perform the correct calculation of the address accounting for signed arithmetic” (from here<\/a>, where these suffixes and are documented).<\/p>\n
The halfword is then written to the address stored in gpr2.<\/p>\n
3. Register to register<\/h3>\n
#movl %eax, %ebx\r\nori 3,0,0\r\n<\/pre>\n
Like SPU, register copy can be done with Or Immediate against zero.<\/p>\n
4. Memory to register<\/h3>\n
#movl Int32, %eax\r\n\r\nlis 4,Int32@ha\r\naddi 4,4,Int32@l\r\nlwz 5,0(4)\r\n<\/pre>\n
Easy enough — load the address, load from the address.<\/p>\n
5. Register to memory<\/h3>\n
#movb $3, %al\r\n#movb %al, ByteLocation\r\n\r\nli 6,3\r\nlis 7,ByteLocation@ha\r\naddi 7,7,ByteLocation@l\r\nstb 6,0(7)\r\n<\/pre>\n
Again, load the address, store a byte to the address.<\/p>\n
6. Register to indexed memory location<\/h3>\n
#movl $0, %ecx\r\n#movl $2, %edi\r\n#movl $22, IntegerArray(%ecx,%edi , 4)\r\n\r\nli 7,2\r\nslwi 8,7,2\u00a0 # extended mnemonic - rlwinm 8,7,2,0,31-2\r\nlis 9,IntegerArray@ha\r\naddi 9,9,IntegerArray@l\r\nlwzx 10,9,8\r\n<\/pre>\n
Load an element offset, shift to get the byte offset, load the address and use the x-form Load Word to fetch from the (base address + offset).<\/p>\n
(The z in that mnemonic refers to zeroing of the upper 32 bits of the 64-bit register.\u00a0 There appears to be an algebraic load that does sign extension)<\/p>\n
7. Indirect addressing<\/h3>\n
#movl $Int32, %eax\r\n#movl (%eax), %ebx\r\n\r\nlis 11,Int32@ha\r\naddi 11,11,Int32@l\r\nlwz 12,0(11)\r\n\r\n#movl $9, (%eax)\r\n\r\nli 13,9\r\nstw 13,0(11)\r\n<\/pre>\n
More of the same kind of thing because that’s how PPC does loads and stores.<\/p>\n
Concluding thoughts<\/h2>\n
Reasonably straightforward, a bit more limited than ia32 in addressing modes but nothing too surprising.\u00a0 Particularly compared to SPU.<\/p>\n
PPC does appear to have some more interesting load and store instructions that I haven’t tried here — updating index on load\/store stands out as something I’d like to take a closer look at.\u00a0 The PPC rotate and mask instructions look like some mind-bending fun to play with, but that’s something for another time.<\/p>\n
Previous assembly primer notes\u2026<\/h3>\n
Part 1 \u2014 System Organization \u2014 PPC<\/a> \u2014 SPU<\/a>
\nPart 2 \u2014 Memory Organisation \u2014 SPU<\/a>
\nPart 3 \u2014 GDB Usage Primer \u2014 PPC & SPU<\/a>
\nPart 4 \u2014 Hello World \u2014 PPC<\/a> \u2014 SPU<\/a>
\nPart 5 — Data Types — PPC & SPU<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"
These are my notes for where I can see PPC varying from ia32, as presented in the video Part 6 \u2014 Moving Data. There are notable differences between PPC and ia32 when moving\/copying data around, although not as much as is the case with SPU — PPC copes with non-natural alignments (although I’m not sure … Continue reading “Assembly Primer Part 6 \u2014 Moving Data \u2014 PPC”<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[5,26],"tags":[38,39],"_links":{"self":[{"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/posts\/724"}],"collection":[{"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=724"}],"version-history":[{"count":11,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/posts\/724\/revisions"}],"predecessor-version":[{"id":736,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=\/wp\/v2\/posts\/724\/revisions\/736"}],"wp:attachment":[{"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=724"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=724"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/brnz.org\/hbr\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=724"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}